2021 Event Gallery

Terms & Conditions

1. Scope of Agreement

• These are the conditions of the contract between you, the Client (“You” and “your”) and Taiwan Semiconductor Executive Summit (“TSES”, “we”, “us” and “our”) governing your use of our services, including event attendance as set out in your booking form. This agreement constitutes the entire agreement between TSES and you. All prior agreements understandings and negotiations and representations (save for fraudulent misrepresentation) whether oral or in writing are cancelled in their entirety. The terms of any other electronic communications will not form part of this agreement.

2. Our Commitment To You

• We will provide you with a planned schedule prior to the Event. Please note that this schedule may be altered where necessary by us.
• We reserve the right to determine the theme, scope and content of seminars and presentations to be held during the Event and to vary the programme and / or its contents as deemed necessary.
• Should the event be cancelled or the location be changed for reasons or circumstances beyond our control we reserve the right to reschedule the Event, including changing the location, and / or withdrawing delegates attendance upon written notice to you. If your attendance is withdrawn by us you will receive a full refund of your registration fee.

3. Delegates

• Only named or pre-agreed delegates may attend the Event. Non–appearance of any of the Delegates will not affect your obligation to pay in accordance with the terms set out below (5). No persons other than those officially registered or agreed with us may attend any part of the Event.
• Delegates must adhere to the deadlines set out by the Operations Manager. Deadlines will be communicated once we have received your delegate contract confirmation. This includes returning your catalogue entry form, delegate photograph and your prioritised meeting request choices.
• Delegates must attend all prescheduled Event meetings and the seminar programme.
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• Delegates are responsible for their own flight, transfer arrangements and accommodation and the costs associated with them.

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• The total fees specified on the Agreement are subject to an additional service charge of 7.5% (“Service Charge”) applied to cover administration costs, and are exclusive of VAT and any other applicable sales tax which shall be payable in addition.
• Payment must be received in full within 28 days from the date of this agreement.
• The applicable VAT rate will be charged in addition to the Total Cost.
• Contracts received within 28 days of the start of the event must be paid by return.

6. Cancellation

• Cancellations received more than twelve weeks prior to the Event commencement date will be entitled to a full refund of the registration fee paid.
• If you cancel your registration less than twelve weeks before the Event commencement date you will incur a charge of £1,500 (less any registration fee, as specified on this registration form, that you may have already paid which will not be refunded).
• Cancellation fees can be avoided by providing replacement delegates from your organisation. You will be liable for any additional cost incurred as a result of supplying replacement delegates. We reserve the right to refuse replacement delegates.
• All cancellations must be received in writing and agreed by us, and full cancellation fees must be paid within 14 days.

7. General

• You the delegate, your executive/s or your agents may not transfer or assign any of the rights or obligations of this Agreement (in whole or part) without our prior consent. Any attempt to resell, assign or transfer rights without our consent will entitle us to cancel the contract without liability to you.
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• This agreement is governed by and will be construed in accordance with English law and each party irrevocably agrees that the courts of England will have the non-exclusive jurisdiction to deal with any disputes arising out of or in connection with this agreement.
• The working language of the Event is English. Delegates requiring an interpretation service must make their own arrangements at their own expense.

Dr. David Haynes

Lam Research, Managing Director of Strategic Marketing, Customer Support Business Group

Biography

David gained a B. Eng and PhD in Materials Engineering from Swansea University. His PhD thesis was in the field of organic semiconductors for electronic and optoelectronic applications. In his professional career, David has accrued more than 20 years of experience in the Semiconductor Capital Equipment and research instrumentation sectors with STS, SPTS and Oxford Instruments. Focused on new technology development, he has a strong process background in plasma tech and deposition for optoelectronics, photonics, MEMS, Power and RF Electronics, as well as advanced chip packaging technologies. Building on this technical knowledge, David has a proven track record in developing strategic business partnerships; specialising in new technology developments and introduction of enabling process capabilities to leading semiconductor fabs worldwide. David Joined Lam Research in June  2016 and is currently Managing Director of Strategic Marketing in Lam’s Customer Support Business Group.

Presentation

Topic: Enabling Specialty Technologies and Advanced Packaging Solutions to Improve the Functionality and Performance of Electronic Systems

As technology node scaling becomes increasingly complex and expensive, an increasing number of semiconductor manufacturers and foundries are turning to the development of specialty technologies and advanced packing solutions to deliver increased system functionality and performance whilst managing development costs.

Specialty technologies such as sensors (MEMS, CIS and IR Sensors), RF Devices, optoelectronics, advanced power semiconductors (MOSFETs and IGBTs), and Bipolar-CMOS-DMOS (BCD) power management ICs are key to enabling applications in consumer electronics, automotive electronics, IoT applications and cellular communications; including 5G. This trend means that by 2023 these specialty technologies will account for approximately 30% of all global IC demand1.

At the same time, this high cost of scaling single ship solutions is also driving development of heterogeneous chip integration using advanced packaging. These heterogenous integration schemes are focussed on bringing together multiple chips and functions in a single package. While conceptually very similar to multi-chip modules, recent developments deploy a strategy of using advanced wafer manufacturing technologies to meet the ever-increasing performance and form factor requirements.

This presentation will talk about the trends in specialty technologies and heterogenous integration through advanced packaging as well as how the technical challenges associated with these applications can be addressed by high volume CMOS manufacturing solutions.

1. IC Insights, McClean Mid-Year Forecast, July 2020 & OSD Report, March 2020

Dr. Wei-Chung Lo

ITRI, Deputy General Director of Electronic & Optoelectronic System Research Laboratories (EOSL)

Biography

Dr. Lo received his Ph.D. from National Taiwan University, and joined Industrial Technology Research Institute to work in advanced electronic packaging, such as 3D IC/3D stacking, fan-out, heterogeneous integration technology for more than 20 years, 85papers, and 27 patents granted.

Dr. Wei-Chung Lo’s major research interests are advanced packaging, intelligent power module, embedded chips in Flex/substrate (Chip in film/substrate), heterogeneous integrated module, and now especially, he is the leader of heterogeneous integration (AI on Chip project, 3D fan-out interconnect/3D SiP program) in ITRI and chief secretary of the Heterogeneous Integration consortium, Advanced Stacked-System Technology and Application Consortium (Ad-STAC), a multinational research association led by ITRI. Currently, he serves as the chairman of Technology working Group of IoT chapter, Heterogeneous Integration Roadmap (HIR).

Presentation

Coming soon…

Kevin Kuo

NI, GM Taiwan Branch

Biography

Kevin Kuo graduated from Queen’s University Canada with a Honored bachelor degree in Computer Engineering. He have 17 years of experience at NI, started from Applications Engineer and moved through several roles including Sales, System Engineering, and Marketing. He have marketing management experiences in China and Taiwan, also having sales management experiences at APAC level. He currently manages key accounts and act as general manager for NI Taiwan.

Presentation

Topic: The Future of Semi Test – Applying Digital Transformation Technologies to Semiconductor Product Development

Digital transformation applies not only to IT organizations, e-commerce, or data clouds, but also to technologies that improves how semiconductor organizations design, test, and manufacture semiconductor products.  In this presentation, we will share the latest trends and technologies that best-in-class semiconductor companies are using to accelerate and improve product designs.  More specifically, we will discuss examples of how companies are leveraging technologies ranging from remote automation to clouds and AI in order to transform modern engineering labs and enterprises.

Markus Rossi

ams AG, VP, Head of Innovation Office

Biography

Markus Rossi has a master degree in physics and a PhD in micro-optics. He was co-founder of the company Heptagon which developed into a major supplier for micro-optical solutions in mobile phones and smartphones. Heptagon was acquired by ams early 2017 where Markus has built up an interdisciplinary team for 3D system solutions. He is now head of the Innovation Office of ams AG.

Presentation

Title: VCSEL Innovations for 3D Sensing Applications & Technologies

VCSELs (vertical cavity surface emitting lasers) are key components for various 3D sensing applications. Innovations in various aspects of VCSEL design, manufacturing, packaging and module technologies have been ignited by the on-going rapid deployment of 3D sensing use cases in consumer and automotive products. This talk outlines some of the key challenges, recent solutions and an outlook to next generation products.

Koushik Banerjee

Intel, VP Technology and Manufacturing Group

Biography

Koushik Banerjee is a vice president in the Technology and Manufacturing Group at Intel Corporation and leads assembly and test technology integration. He is responsible for developing innovative, industry-leading packaging technologies for Intel products and transferring those technologies successfully into high-volume manufacturing. Banerjee collaborates with business units and product design teams to set a packaging roadmap that assures both technology leadership and affordability, with a focus on operational excellence in technology development program execution.

Banerjee joined Intel as a packaging design engineer in 1991, shortly after completing graduate school. During the first 10 years of his Intel career, he held various management and leadership positions in packaging design, in the course of which he helped introduce several novel technologies. In 1996, his work on the successful transition from ceramic to organic packaging for microprocessors earned him an Intel Achievement Award. From 2002 to 2005, as substrate technology research line manager, Benerjee was responsible for path-finding in next-generation substrate and interconnect technologies. From 2005 to 2011, he served as the director of assembly module engineering, overseeing the development of next-generation packaging assembly technologies.

Banerjee holds more than a dozen patents in the field of microelectronic packaging. He earned his bachelor’s degree in mechanical engineering from Jadavpur University in India and his master’s degree in mechanical engineering from Georgia Institute of Technology.

Presentation

Topic: Packaging Innovations

This talk will cover packaging innovations that are critical to enable complex products and the associated challenges. Heterogeneous integration is a key driver in today’s packaging research and is a rich field for new inventions. Innovations will need to com from all aspects-design, architecture, process and also supply chain. As companies pursue silicon disaggregation and heterogeneous integration the challenge for packaging technology developers will be to come up with innovations that gracefully re-aggregate so its doesn’t appear that we partitioned things to begin with. And all of this has to be done with product affordability in mind.

Chiang Fu

SVP Design Verification, GUC

Biography

Chiang Fu is Senior Vice President of Global Unichip Corp. He joined GUC from 2008 as Product, Package design and testing develop director for 40nm and 28nm ASIC production. In 2015, He is also in charge of GUC SOC RD for 12nm and 7nm SOC spec-in design and verification. He has published 3 conference papers as corresponding author and granted 5 patents in USA , Taiwan and China. He is also the member of the SEMI Taiwan package &Testing committee since 2015.
His previous positions include the department manager of 8 and 12 inches yield and process engineering, TSMC(1993-2008).

Presentation

Topic: Enabling AI and Networking products by 2.5D/3D advanced package

The integrated circuit two-dimensional scaling is slowing down at 5nm FinFET technology. More and more chip designs adopt chiplet, 2.5D and 3D stack solutions to extend the Morre’s Law with gains in chip performance, power and cost. Besides the proven 2.5D D2D solution, GUC will provide GLink-3D as 3DIC integration solution in the near future by TSMC advanced SoIC and WoW packaging technologies.

Justin Huang

Micron, Director Advanced Packaging Technology Development

Biography

Justin Huang is Director of Advanced Packaging Technology at Micron. He has 12+ years experience and technical depth in various areas of semiconductor packaging. He started his career at Nanya PCB for advanced substrate technology and later joined TSMC for 3DIC packaging. While at TSMC, he was involved in the development and qualification of Chip on Wafer on Substrate (CoWoS) and Integrated Fan Out (InFO) advanced packaging technologies across various customers. At Micron, he has been instrumental in developing HBM and technology transfer into manufacturing. Justin Huang graduated from National Cheng Kung University with a master degree in Chemistry.

Presentation

Topic: Advanced Packaging – Now and Future

As one of the leading memory company, what is the advanced packaging of Micron today and what are future opportunities? Deep industry engagement in specific critical area for technology acceleration is necessary for next generation package. Here we will define key areas of opportunities that require industry collaboration and focus.

Dr. Roman Ostholt

LPKF, Managing Director Electronics

Biography

• RWTH Aachen University 2002-2007 Dipl.-Ing. Mechanical Engineering
• RWTH Aachen University 2007-2011 Dr.-Ing. Mechanical Engineering
• Fraunhofer Institute for Laser Technology 2007-2011
• Joined LPKF as Innovation Manager in 2011
• Group Technology Manager 2014-2018
• Vice President LIDE since 2018
• Managing Director of the Business Unit Electronics starting 09/2019

Presentation

Topic: Laser Induced Deep Etching of Glass- New possibilities in Advanced Packaging

Glass is a material with many advantages for Advance Packaging applications. However, it is considered to be processable only with strong limitations. The shortcomings of conventional glass processing have unjustly earned glass the reputation of being difficult. With Laser Induced Deep Etching, a new processing method is now being introduced that removes the limitations of current manufacturing processes and thus reveals the full potential of glass in microsystems technology. The talk presents the basics of Laser Induced Deep Etching of Glass and gives an overview of industrial applications in the field of Advanced and Wafer Level Packaging.

Damon Tsai

Onto Innovation, Product & Marketing Director, Inspection BU

Biography

2018-2020 ONTO Innovation (Rudolph Technologies), Global Director of Inspection Product Management
2D/3D inspection and metrology solution for Advanced package, FEOL macro, RF, Power and CIS market

2015-2018 Ultratech, Asia Product Director of Inspection System

In-line 3D wafer shape inspection for VNAND/DRAM/foundry process control

2011-2015 KLA, Product Marketing Manager/Application
Defect inspection for compound semi, VCSEL and HB-LED

Presentation

Topic: Inspection solutions for next-generation packaging challenges

The demand for AI, 5G and HPC drives the complexity of packaging technology, heterogeneous integration, 3D stacking, large packaging size, fine pitch RDL and micro bump/pad brings the new process challenges and requires more advanced 2D/3D inspection solution for process control to improve the device yield and reliability.

Onto Innovation is a leader in process control, combining global scale with an expanded portfolio of leading-edge technologies that includes macro defect inspection of wafers and packages; metal interconnect composition; factory analytics; and lithography for advanced semiconductor packaging.

Shai Cohen

proteanTecs, Co-Founder & CEO

Biography

Shai Cohen is an entrepreneur and industry veteran, with vast experience in building technology companies from the ground up. Prior to founding proteanTecs, Shai co-founded Mellanox (NASDAQ: MLNX), a global leader of end-to-end InfiniBand and Ethernet interconnect solutions for servers and storage. He served as Mellanox’s Chief Operations Officer from 2011 and before that as VP of Operations and Engineering, from 1999. While at Mellanox, Shai oversaw all internal operations and production, and co-led the company’s research and development activities. He served as a member of the Mellanox Board of Directors from 2015 to 2018. From 1989 to 1999, Shai worked at Intel Corporation, where he was a senior staff member in the Pentium processors department and a circuit design manager in the cache controllers group. Shai holds a B.Sc cum laude in Electrical Engineering from the Israel Institute of Technology, Technion.

Presentation

Topic: Predictive health and performance monitoring with Universal Chip Telemetry™ (UCT)

The semiconductor industry is ready for the next phase of its evolution, entering the era of deep data. To cope with the rising uncertainties associated with advanced electronics, the fragmented nature of the industry and the limited visibility in today’s best-known-methods, a paradigm shift is needed in the way data is sourced, correlated and used. Universal Chip Telemetry™ (UCT) is proving to be a must-have technology for companies who want to stay ahead of the curve, providing predictive health and performance monitoring, from design to field. It creates a common data-language throughout the value chain, based on fusion and inference of on-chip measurements. Users gain insights and alerts on a cloud-based analytics platform, allowing them to take immediate action to maximize profit, ensure supply and improve performance, quality and reliability – all while reducing costs.

Dr. Mike Ma / 馬光華博士

Amkor, President Taiwan / 艾克爾國際科技, 台灣區總經理

Biography

Mike Ma joined Amkor in 2017 and is currently President, Amkor Technology Taiwan. He has more than 29 years of experience in the semiconductor industry, including positions with SPIL, United Microelectronics Corporation (UMC) group, WaferTech LLC (now a TSMC company) and the Institute of Microelectronics (IME) of Singapore. Mike holds a Ph.D. Materials Science & Engineering, North Carolina State University, USA and a M.S. from Northeastern University, Boston, MA, USA.

Presentation

Topic: Advanced Packaging Trends in Semiconductors

The semiconductor industry is at a critical junction where advancements in 5G, IoT, Networking and Automotive segments are dependent on our industry to provide a viable solution. Many of these potential options are ‘system based’ solutions, where the whole system needs to meet the requirements of the application. Packaging is an integral part of designing these complex solutions. Semiconductor packaging has become more critical as process geometries have shrunk and performance and thermal challenges depend heavily on packaging characteristics and materials. Advanced packaging is also critical in other emerging markets such as AI, data centers, high performance computing, infotainment and autonomous driving. Outsourced Semiconductor Assembly and Test (OSAT) companies play a crucial role in creating value by partnering with our customers to provide engineering innovation, develop a sustainable supply chain of materials and invest in scalable manufacturing and test to enable and deliver these products.

This presentation will discuss the trends and challenges of the advanced packaging ecosystem and the value creation role OSAT’s play.

Giuseppe Izzo

Regional Vice President and Taiwan Managing Director, STMicroelectronics’ Asia Pacific Region.

Biography

Izzo joined SGS-Thomson Microelectronics (now STMicroelectronics) in 1987 and shortly thereafter relocated to Asia, living and working in many different Countries, from Korea to Taiwan, to Hong Kong to China. He has held various positions within ST’s Asia Pacific organization, covering marketing, application development and product design for power management, consumer and computer systems, automotive, and multi-segment products. Izzo established ST’s Automotive and Multi-Systems Competence Centers in Shanghai and Power Management Competence Center in Taiwan, contributing to the Company’s success in in many areas of the business developments in Asia Pacific, while leading the expansion of the operations in Taiwan.

Starting 1991, Izzo has been working in Taiwan where he has intermittently lived for more than 20 years. He is married with a Taiwanese lady, with two children.

For the year 2013 and 2014, Izzo served as the Chairman of the European Chamber of Commerce Taiwan (ECCT). In the Years 2015, 2016, 2017, 2018, Izzo served as the Vice Chairman of ECCT. In year 2019 and 2020 Izzo has been elected again Chairman of the ECCT.

Other activities include:

• SEMI Taiwan: Vice Chairman of MEMS Committee from 2013
• Delegate of the Italian Academy of Cuisine in Taiwan from 2018
• Industrial Advisory Board POLITO – SCUT* in 2015 and 2016
• American Club Board of Directors from 2016 to 2018
• Taiwan Telematics Industry Association Board of Directors from 2014 to 2017

In January 2019 Izzo was conferred the Taiwanese Citizenship, for Special Merits.

Giuseppe Izzo was born in Caserta, Italy, in 1958 and graduated with a degree in Electronic Engineering from the University of Naples, Italy.

*POLITO: Polytechnic of Torino (Italy), SCUT: South China University of Technologies in Guangzhou

Presentation

Topic: The future of Power

Chih-I Wu

ITRI, VP and General Director, Electronic and Optoelectronic System Research Laborations

Biography

Dr. Chih-I Wu is the VP and General Director of Electronic and Optoelectronic System Research Laboratories, Industrial Technology Research Institute (ITRI), as well as a professor in Graduate Institute of Photonics and Optoelectronics and Department of Electrical Engineering of National Taiwan University. His research focuses on photonic and electronic devices, organic light emitting materials, metal-semiconductor interfaces, and heterojunctions. Prior to joining NTU, he worked at Component Research Lab of Intel in the US from 2000 to 2004. His work at Intel was mainly on developing the advanced VLSI process technology, such as Cu and low k interconnects, metal gate materials, and atomic layer deposition process.

Dr. Wu got his B.S. degree from National Taiwan University and M.S. degree from Northwestern University, both in Physics. He received his Ph.D. from Princeton University in Electrical Engineering. Dr. Wu has published more than 200 journal papers in both organic and inorganic semiconductor devices.

Presentation

Topic: New wave of semiconductor: AI on Chip and Heterogeneous Integration

Gaurav Kaul

Hewlett Packard Enterprise, Senior Architect HPC/AI

Biography

Gaurav Kaul is a senior architect focused on HPC and AI customers in HPE. He has worked extensively in these areas in IBM, Intel and Amazon Web Services (AWS) for the last 7 years. In his current role Gaurav works with HPE customers on convergence of AI and HPC and how hardware and software infrastructure will look like to fulfill the customers’ technical and business requirements. In addition, Gaurav works with HPE partners in semiconductor and software space for technical alignment and roadmap planning.

Presentation

Topic: Convergence of AI, HPC and Exascale – How it will drive computer architecture and semiconductor technology

AI workloads driven by the rise in popularity of deep learning are now being increasingly run on HPC infrastructure, both on-prem and cloud. At surface level this convergence may be seen due to the reliance on accelerators for AI workloads such as GPUs and ASICs. While at hardware level, deep learning and exascale computing is leading a renaissance in new hardware development, even more impact can be expected when deep learning algorithms are used in simulations for HPC. Building a hardware and software stack for AI and Exascale which is energy efficient and support current software stacks is hard engineering problem. In this talk we look at some technologies on the horizon including storage class memories, optical networking and interconnects, and near data processing which can allow us to scale compute performance as per Moore’s law while the semiconductor technology slows down to some extent while going to 5nm and lower nodes

Dr. Mallik Tatipamula

Ericsson, CTO

Biography

As a CTO at Ericsson, Dr Mallik Tatipamula leads evolution of Ericsson’s technology and champion the company’s next phase of innovation and growth. Prior to Ericsson, he held several leadership positions at F5 networks, Juniper networks, Cisco, Motorola, Nortel and Indian Institute of Technology (Chennai). During 30 years of his professional career, he has played a very unique leadership role in delivering industry’s most powerful innovations, standards contributions, products/solutions, design implementation of early real-world deployments working with telecom operators, and also innovating for the future, working with academia, by anticipating what might happen next, to accelerate the architectural transitions in the telecom industry. He has identified strategic opportunities, and implemented programs that have brought world-leading innovations to the telecom sector with a multi-billion dollars impact, launching over 50 products/solutions that are deployed in global telecom networks to enable these major network transitions from 2G to 5G.

Since 2011, he has been a visiting Professor at King’s College London. He is a Fellow of Canadian Academy of Engineering (CAE) and The Institution of Engineering and Technology (IET, UK). He received Univ. of California, Berkeley’s Garwood Center for Corporate Innovation Award in 2019, “CTO of the year” award by Total Telecom World Communications Awards (WCA) for the year 2020 and also “IET Achievement medal in telecommunications for the year’2020”. He has Ph.D. in Information and Communications Engineering from the Univ. of Tokyo, Japan, Master’s in Communication Systems from Indian Institute of Technology, Chennai, India and Bachelor’s in Electronics and Communications Engineering from NIT, Warangal, India. He mentored over 100 undergrad/graduate students, delivered 400+ keynote/invited talks/tutorials/lectures, co-authored 2 books, 100+ publications/patents, served on 30+ IEEE conferences committees. He has been involved in developing industry-academia partnerships in Canada, US, UK and India for future technology innovations. He serves on several advisory boards including Global Semiconductor Alliance, Gartner/Evanta CIO Council, Digital India Initiative, London Digital Twin Research Center, and Chair for the Industry Advisory Board for Garwood Center for Corporate Innovation and Center for Growth Markets at Univ. of California, Berkeley.

Presentation

Topic: Harnessing the power of 5G, Edge Computing & AI/ML for IoT applications

This session begins with an update on 5G technology, standards and global network rollouts. Then it will present future technology evolution and research challenges at the intersection of “5G, edge computing and AI/ML” for realizing distributed multi-cloud to address Industrial IoT applications. It will conclude with a discussion on research opportunities over next decade for 5G and beyond.

Jimmy Lin

General Manager of Taiwan Branch, National Instruments

Biography

Jimmy Lin currently serves as general manager for NI Taiwan. In his 18 years career with NI, he experienced various engineering, sales, and managing his team to serve semiconductor, electronics manufacturing, and academia customers. He holds master degree of material science and engineering from National Chiao-Tung University, bachelor degree from National Taiwan University, and three LED process related patents (USA/Taiwan).

Presentation

Title: The Future of Semi Test – Applying Digital Transformation Technologies to Semiconductor Product Development

Digital transformation is going apply not only to IT organizations, e-commerce systems, or storage data in the cloud but also to many technologies that improve our experiences how semiconductor organizations design, test, and manufacture semiconductor products. In this presentation, we’ll share some of the latest trends and technologies that best-in-class semiconductor companies are using to accelerate and improve product designs. More specifically, we’ll share practical examples of how companies are utilizing technologies ranging from the remote automation to the cloud to artificial intelligence to transform modern engineering labs and enterprises.

Dr. Marvin Liao / 廖德堆博士

Vice President / 副總經理
APTS / 先進封裝技術暨服務
tsmc / 台灣積體電路製造股份有限公司

Biography

Education

Ph.D. Materials Science, University of Texas at Arlington, USA, 1989

Bachelor Materials Science, Tsing Hua University, Taiwan, 1979

Experience 

tsmc Advanced Packaging Technology and Service, 2011 – now

tsmc Special Project, 2009 – 2010

tsmc Fab 6 Director, 2003 – 2009

Chartered Semiconductor, Singapore, 1997 – 2002

Applied Materials, USA, 1994 – 1997

SGS Thomson Microelectronics (STM), USA, 1990 – 1994

Presentation

Topic : 3DFabricTM for System Level Innovation

3DFabricTM is an integrated SoICTM frond-end chip stacking and back-end advanced packaging solution developed to meet future HPC and 5G system need.

In this solution SoICTM chip stacking technology provides cost and performance for future leading node chiplets integration. The fine pad pitch capability in SoICTM can unleash the innovation for chiplet integration to reach highest performance. CoWoS® advanced packaging with 3 types of interposer, silicon, RDL and LSI (local silicon interconnect) offer the best 2.5D packaging solution for large size package with HBM integration, fine pitch capability, reliability, and cost.

A 3DFabricTM Intelligent Fab with AMHS automation, production traceability, big data analysis, and precision process control to achieve faultless manufacturing will be built for SoICTM production and quality need in the near future.

Hitoshi Mizunuma

Assistant General Manager, Toshiba Electronic Components Taiwan Corporation

Biography

Dr. Hitoshi Mizunuma is an Associate General Manger of System Device and Digital Marketing Department of Sales Management & Semiconductor Division at Toshiba Electronics Components Taiwan Corporation, serving as a marketing engineer in charge of mixed signal ICs, logic LSIs, and discrete products of AIoT, IIoT, and IoV edge device application fields for more than 20 years in Taiwan. He earned both bachelor and master degrees in mechanical engineering at Tokyo Institute of Technology, and earned a Ph.D. degree in computer science and information technology at National Taiwan University.

Presentation

Topic: Re-inventing MCUs: from Micro-Control Unit to Motor-Control Unit

There are only two silicon choices in the market for FOC (Field-of-Control) inverter system design: (i)  faster ARM Cortex core to execute all algorithm by software, or (ii) hard-wired logic to optimize the design metric at the expense of poor flexibility and upgradability.  Toshiba proposes the 3rd way “Vector Engine” integrated MCUs to find the best trade-off between two options, introducing the industry-first turnkey solution of not only MCUs but also Power MOSFETs, photo-isolators and development tools required for various high-wattage motor applications.

Andy Chuang

President, Episil Technologies Inc.

Biography

Mr. Chuang received his M.S. degrees in Electrical Engineering of National Tsinghua University, Taiwan. After graduated, he joined UMC R&D to start his professional career. Starting from R&D to give him sold knowledge in wafer manufacturing. Technical Marketing let him connect wafer manufacturing and product application jointly. Gradually involving sales and expat to Europe to manage key customers. Completely training to make him realize wafer business and supply chain. After UMC, he joined EDA vendor, Synopsys. This experience helped him connecting chip design to wafer manufacturing. After that, he joined CSMC in China as VP of marketing and sales. He led company to have creative ideas to customize BCD processes targeting to specific application and won the China market, such as Class A/B, Class D, Charger, PMIC, LED display, and LED lighting. In 2013, he joined Episil in Taiwan, started business in compound semiconductor (SiC and GaN-on-Si). Episil is a professional partner in power devices to provide both SiC and GaN-on-Si foundry service.

Presentation

Topic: WBG Industrial Overview & Technologies

Energy saving and carbon reduction are major topics in the environment protection of earth. WBG technology is one of best solution to enhance the efficiency of energy conversion. PFC in power supply, PV inverter in solar application, charging system (OBC, inverter, DC/DC) in xEV industry, Wireless Power, LiDAR in autonomous car, which stimulate and drive WBG adoption in those emerging market. Device manufacturing mostly bases on existing Si-based Fabs, it created complexity to balance cost, productivity and efficiency. Stand on chip maker’s demand, Episil Technologies Inc. provide one-stop shop to accommodate customer to design his own product. To catch rapid business and enhanced competiveness, Episil provide a promising cycle time for wafer manufacturing, and continue process roadmap for further product development. It is best choice for those who require SiC foundry.

Yu-Po Wang

R&D Senior Director, SPIL

Biography

Wang Yu-Po received Ph.D. in Mechanical Engineering from State University of New York at Binghamton, U.S.A

In 1997, he started career at Gintic Institute of Manufacturing Technology in Singapore. He has jointed SPIL since 1998 and led the R&D advanced packaging design team for leadframe, substrate and wafer form packages development.

Dr. Wang has strong knowledge and experience in packaging characterization including thermal/ electrical simulation, advanced material(co-development), design and advanced packaging development. He has 83 patents in US.

Experience:

• 1997-1998 Gintic Institute of Manufacturing Technology, Singapore
• 1998-Present SPIL, Taiwan

Ehsanul Islam

Senior Director of Engineering, Qualcomm

Biography

Ehsanul Islam is a senior director of engineering at Qualcomm and responsible for Taiwan & SEA customer engineering teams including HW, SW and Technical account managers.

Prior to joining Qualcomm in 2013, Ehsanul Islam worked in executive level positions for PacketVideo (a sister company of NTT DoCoMo) and Vodafone Japan with a strong history in program management, defining and managing product roadmaps for multimedia software and mobile platform for high end smartphones. Since 2009, He served as a managing director of PacketVideo India with responsibility for building up the high-quality engineering team for new multimedia software development including product definition and rollouts as well as strategic customer engagement and alignment.

Ehsanul Islam has also held application engineering positions at Motorola/Freescale semiconductor, and Agilent Technologies, focused largely on wireless communications. He holds a bachelor & master`s in electronics engineering from the Tokyo University of Electro-communications and MBA in international business from the Tsukuba University, Japan.

Presentation

Title: The 5G Future

Qualcomm is leading the world to 5G. We are designing a unified, more capable 5G platform by inventing many new technologies to meet 5G’s expanded and radically diverse connectivity requirements. We are driving 5G NR from standardization to commercialization, contributing to 3GPP standards.

From 2019, 5G moved from a buzzword to a reality as 5G-enabled smartphones began to hit the market and carriers started offering 5G services. That’s just the beginning. It will be a platform for innovation in ways we cannot yet imagine. What’s next for 5G and key enabling technologies that will enhance the 5G experience moving forward?

Silvan Wuethrich

Head of Semiconductor Business Unit, Evatec

Biography

Silvan Wuethrich gained his bachelor degree in micro and nanotechnology at NTB, Buchs, Switzerland specialising in the field of oxide and nitride layers for optical interference coatings for his thesis. After holding various management positions within Evatec he took over as Head of Business Unit “ Semiconductor”  in April 2018 with overall responsibilty for Evatec’s activities across Power Device, MEMS and Wireless Technology Markets

Presentations

Title: Clever machines – getting the most from the Fab

Semiconductor production sites no longer need human intervention to manage every aspect of their production. Today, an increasing number of industrial processes are supported by automation, artificial intelligence (AI) and other upcoming technologies like the IoT that enable organizations to get more out their production lines.

Clever predictive maintenance technology is an effective way to avoid potential failures and costly production loss. The final outcome is less downtime, less money spent on repairs, and less human effort in managing all of these maintenance and service processes.  The newest generation of Evatec PVD systems address such future requirements of semiconductor fabs driving down production costs.

Ruurd Boomsma

CTO, Besi

Biography

Ruurd Boomsma received a Master Degree in Technical Physics from the State University of Groningen, the Netherlands, in Semiconductor Physics and High Vacuum Technology. He started working in the equipment part of the semiconductor industry in 1984 at ASM in Bilthoven, the Netherlands, in front end equipment including Epi, Diffusion, PECVD Implant and Litho and was also involved in the sales of the first steppers from ASML (at that time part of ASM). Then he moved on to MRC, a USA based company for PVD and Etch equipment. Later he became responsible for the Unaxis (Oerlikon) Materials and Display Divisions. He is now over 10 years active at Besi. Initially involved in technology assessment, supply chain optimization followed by holding the responsibility for the Plating Product group and later full responsibility for the Die Attach product group. He is now Besi’s Chief Technology Officer and also responsible for strategic supply chain management and overall quality.

Presentation

Title: Advanced Packaging Technologies for next generation devices

The drive towards faster response semiconductor devices requiring lower power consumption and yielding higher overall performance coupled with smaller features is continuing and even accelerating, enabling new applications like 5G, AI, Cloud Computing and Autonomous Driving. New packaging technologies like 2.5D, 3D, SIP and Chiplets are becoming a key enabler now. In addition, the upcoming 5G technologies also require new packaging technologies

This presentation will highlight some of the latest technical developments and limitations on placement and bonding technologies for Flip Chip, TCB and direct Cu to Cu Bonding on Die Level. New levels of accuracy, placement speeds and cleanliness are key factors for such processes. Also we will highlight SIP and advanced molding for 5G and other devices.

At last we will also review some of newest developments in advanced packaging for power devices driven by car electrification as well as demands for more energy efficient power conversion

Chuck Huang

Senior AVP Technical Marketing, Win Semi

Biography

Coming soon…

Presentation

Title: Compound Semi. in Wireless Communication: Opportunities & Challenges

With the advent of the post-5G era, there is still a lack of the discussions about the requirements for post-5G specification, feature and technology. Currently, what we can expect is that the specifications of frequency and linearity will be a challenge for semiconductor technology.

Due to excellent physical properties, compound semiconductors have been widely used in communication and other related applications. In this talk, we will propose the evolution of roadmap and trends from the perspective of technologies and applications. Moreover, we will try to explore the opportunities and challenges for future communications as well.

Cheng-Kuang Lee

Senior Solution Architect, Leader of NVIDIA AI Technology Center – Taiwan, Nvidia

Biography

2018-now senior solution architect, leader of NVAITC-TW (NVIDIA AI Technology Center – Taiwan)

2016-2018 principle engineer of YEP (Yield Excellence Program) in TSMC

2012-2016 assistant professor of EE department of Chang Gung University (CGU).

2010-2011 Post-doc in Graduate Institute of Photonics and Optoelectronics(GIPO) of National Taiwan University (NTU)

He received the B.S degree in Physics in 2003, and the PhD degree in 2010 from GIPO, both from NTU.

His research and scientific interests include deep learning and machine learning algorithm development, Medical or Industrial imaging system, like Optical Coherence Tomography/Microscopy, ultrasound, MRI, CT etc.

Presentation

Title: NVIDIA Deep Learning Relevant Creativity in EDA fields

Deep Learning revolutionizes many fields like medical, autonomous, manufacturing, finance, electronic design automation (EDA) etc. In this talk, we will give you a briefing about deep learning and select two deep learning innovations related EDA field including (A) Graph Convolutional Network in Testability Analysis and (B) DREAMPlace.

Akshay Singh

Vice President Advanced Packaging Development, Micron

Biography

Dr. Akshay Singh is Vice President of Advanced Packaging Technology Development at Micron. He joined Micron in 2006. He leads a global team that is responsible for delivering advanced memory packaging solutions for compute, storage, mobile and embedded markets. Prior to joining Micron, Akshay worked at a startup developing actuators and sensors based on novel electroactive polymers. Akshay holds master and doctoral degrees in mechanical engineering from Louisiana State University in US and bachelor degree in mechanical engineering from Maharaja Sayajirao University in India.

Presentation

Title: Accelerating Innovation with memory and storage solutions

Data is the currency of the new Data Economy driving value creation not imagined only a few years ago. With unprecedented data explosion, Memory and storage solutions are becoming key to unlocking finance insights and powering health care, transportation and communication. Innovation in compute architectures, silicon solutions and heterogeneous integration will be at the center of this transformation.

Pei Lin Pai

VP VP of Technology R&D Group, Winbond

Biography

1981 B.S. National Taiwan University, EECS
1987 Ph.D., UC, Berkeley, EECS

1987-1989 Intel Corp. Sr Process Engineer
1989-1990 Cypress Semiconductor Corp. Engineering Manager
1991-1993 Knights Technology, VP, Engineering
1993-1995 Omega Micro Inc. VP, Engineering
1995-1999 Vanguard International Semiconductor Corporation, Director of Marketing
2000-2003 Ascend Semiconductor Corp. Founder and President
2003-2012 Nanya Technology Corporation, VP, Global Sales and Marketing
2012-2014 FocalTech Systems, VP, Marketing BG
2014-   Winbond Electronics Corp. VP, Technology R&D Group

Presentation:

Title: Taiwan Memory Industry’s Future: Hidden Champion

In this presentation, we will review the limitation of Taiwan’s memory industries, for both DRAM and Flash. The Fundamental issues are lagging technologies, which make the typical memory companies’ strategies not working. However, if we utilize the advantages from our strength, more dynamic industries with smaller scale, there are opportunities for us to thrive to prosperity. The path is generally described as the Hidden Champion.

The Hidden Champion approach requires the company to excel in the selected industry segments with leading advantages, from technologies, business strategies, or customer service. These advantages will only come from consciously building up through the years until some entry barriers are established.

In addition, the Hidden Champion also typically survey the global market to expand into unique market segments where its unique strength delivers unfair advantages for the companies. Also the Hidden Champion is best utilizing the global resources especially talents.

Frankwell Lin

President, Andes Technology

Biography

President Lin started his career being as application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own chip products, he experienced engineering, product planning, sales, and marketing jobs with various product lines in UMC. In 1995, after four years working on CPU chip product line as business director, he was transferred to UMC-Europe branch office to be its GM when UMC reshaped to do wafer foundry service, he lead UMC-Europe to migrate itself from selling IDM products to selling wafer foundry service.

In 1998, after 14 years working in UMC, President Lin switched job to work in Faraday Technology Corporation (Faraday), he lead ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR), as well as Faraday’s spokesperson, in 2004, he started to lead the CPU project spin off operation of Faraday. President Lin became co-founder of Andes Technology Corporation (Andes) in 2005 when it was found up, he formally took position to be Andes’ President since 2006.

President Lin received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA. Under his management, Andes has been recognized as one of leading suppliers of embedded CPU IP in semiconductor industry. Andes also won the reputation of leading technology company with awards such like 2012 EE Times worldwide Silicon 60 Hot Startups to Watch, 2015 the Deloitte Technology Fast 500 Asia Pacific award, etc.

In 2015, President Lin received accolade award of Outstanding Technology Management Performance, Taiwan, for his contribution to the high-tech industry.

Presentation

Title: From Edge to Cloud: RISC-V with DSP, Vector and Custom Instructions for AI

Edge and Cloud Computing are in the corner, getting popular, yet their implementation are emerging and new designs are on the way to production. In this presentation, Andes RISC-V Cores with extensibility and modularity allowing designers to use RISC-V cores and eco-system for all of the workloads will be introduced. Andes AI customers adopt RISC-V Cores with applications from edge to cloud. An overview regarding how to leverage the RISC-V DSP extension for low-data volume workloads like voice and face recognition with low power will be presented. For high data throughput applications, we will introduce the industry-first commercial RISC-V Vector Processor solution and how it can be used to speed up compute-intensive applications. Then, how to leverage RISC-V’s strength to allow custom instruction extensions by leveraging Andes Custom Extension (ACE) will be introduced.

Ian Hsu

Director, Mediatek

Biography

Education:

Master of Science – Microelectronic Engineering, Arizona State University

Experience:

Deputy Director/ MediaTek

Sr. Engineer/Qualcomm.

Sr. Engineer/Via Technology

Presentation

Title: Emerging Chiplet Package Technologies

Development of Chiplet package technologies from the IC design house point of view

Santosh Kumar

Director & Principal Analyst, Packaging, Assembly, Substrates & Semiconductor Manufacturing, Yole Development

Biography

Santosh Kumar is currently working as Director & Principal Analyst at Yole Développement. He is involved in the market, technology and strategic analysis of the microelectronic assembly and packaging technologies. His main interest areas are advanced IC packaging technology including equipment & materials. He is the author of several reports on fan-out / fan-in WLP, flip chip, and 3D/2.5D packaging. He received the bachelor and master’s degree in engineering from the Indian Institute of Technology (IIT), Roorkee and University of Seoul respectively. He has published more than 40 papers in peer reviewed journals and has obtained 2 patents. He has presented and given talks at numerous conferences and technical symposiums related to advanced microelectronics packaging.

Presentation

Title: Future of Fan-out WLP/PLP business: Myth vs Reality

Fan-out packaging is not new, and it has been adopted in mobile devices for more than 10 years. However, it has attracted lot of attention since 2015, when Apple adopted TSMC’s InFO technology for iphone A10 application processor (AP). It was speculated, other key fabless players will soon adopt InFO or other high-density fan-out technology for flagship mobile AP by replacing laminate substrate-based flip-chip PoP. But it has not happened, even though already qualified by various fabless players. What are the reasons? Do we see other players adopt high density fan-out for mobile AP in near future? After a steady growth, we recently saw the decline in the low-density fan-out (eWLB type) business. What is the current status and prospect? TSMC is clearly emerged as the winner in the high-density fan-out with multiple design offerings. Is there any challenge to them from other OSATs /foundries/IDMs? What is the status of fan-out at other manufacturers? Fan-out PLP has also generated lots of interest and many players are working on it including tool/materials suppliers. Samsung /SEMCO started FO-PLP HVM with Galaxy watch AP. Will Samsung adopt FO-PLP for flagship phone AP? What is the FO-PLP status at other manufacturers (OSATS/IDMs)? Will the FO PLP business significantly increase in the coming years as ASE and PTI increase capex by bringing additional PLP capacity online? This presentation will try to answer these questions and overview the overall activity happening in fan-out WLP/PLP ecosystem.

Peter A. Rabbeni

GLOBALFOUNDRIES, Vice President, Mobility and Wireless Infrastructure (MWI) Business Unit

Biography

Peter Rabbeni joined GLOBALFOUNDRIES in October 2012 and brings over 30 years of design/development, field applications engineering, technical sales, business development and marketing experience in the area of RF systems, circuits and technologies. Mr. Rabbeni is currently the Vice President of Business Line Management for the Mobility and Wireless infrastructure Business Unit at GLOBALFOUNDRIES and is responsible for all business line P&L activities associated with the wireless infrastructure and SATCOM markets.

Peter helped support M&A activity that culminated in the GF acquisition of IBM Microelectronics Specialty Foundry business in 2015. Prior to joining GF, Peter served as WW Business Development Program Director for IBM Microelectronics Specialty Foundry business from 2010 to 2012, where he helped focus the division’s 200mm foundry offerings in capturing silicon content in mobile handset front end modules and created one of the most successful and profitable design-win periods in the divisions history resulting in more than $3B in long-term revenue and to date shipping over 50B RFSOI-based products for smartphone and WiFi front ends.  He joined IBM in 2001 and held various leadership roles in foundry sales, field applications engineering and marketing before heading up the business development and strategy responsibility for the microelectronics foundry business unit.  Prior to IBM, Peter held various RF systems and circuit design engineering positions at Ericsson, Raytheon and the U.S. Army Millimeter Wave Lab.  Peter received his BSEE degree from the Stevens Institute of Technology in 1986 and an MSEE from the University of Massachusetts in 1991.  He is an alumnus of the IBM Executive Management program and the Executive Program for Growing Companies at Stanford University.

Peter has co-authored several papers and published a number of trade journal articles and blogs and speaks regularly on the trends and developments in the mobile wireless technology space at conferences and consortiums across the world.  Mr. Rabbeni is a member of the IEEE.

Presentation

Title: 5G Rising: Technology Choice for Network Differentiation

5G deployments are rapidly being executed across major markets across the world. The use cases and applications aim to drive new applications and business models and potentially add $2T+ to the global economy over the next 15 years. With this benefit comes system complexity that requires careful optimization in its implementation. Coverage and reliability have always been key factors in operator profitability. In fact, the choice of technology used to implement these systems has a direct bearing on not only the customer experience but also operator investment over the life of the network. This presentation will explore the technical and financial tradeoffs on how the choice of specialized silicon solutions can potentially redefine 5G network customer experience and economics.

Mario Morales

Program Vice President, IDC

Biography

Mario Morales is the program vice president of IDC’s enabling technologies, storage, and semiconductor research. He is responsible for in-depth analysis, evaluation of emerging markets and trends, forecasting, and research of major semiconductor industry segments such as embedded and intelligent systems, wireless, personal computing, networking and cloud infrastructure, automotive electronics, and consumer.

Mr. Morales is an accomplished program vice president, manager, and industry expert with over 25 years of experience in building a multinational top-tier consulting, sales, and research team and driving a set of established businesses. Solid experience in managing strategic partnerships and advisory services with IDC’s largest multinational clients. Strong analytical, strategic planning skills, and managing complex projects involving strong collaboration across geographies, functional groups, and business units. Proven leadership skills and instrumental at establishing research and business KPIs.

Mr. Morales is a trusted advisor to leading high tech company executives, financial investors, and bankers on market landscape and direction, product and technology positioning, competitive benchmarking, M&A, HW, and SW technology, and brand health and sustainability. Established relationships with technology suppliers including Intel, Samsung, TSMC, Qualcomm, Huawei, HP, AMD, NVIDIA, Microsoft, Facebook, TI, Micron, IBM, GE software, SoftBank, ARM, NXP, and others.

Mr. Morales is the leading advisor and expert analyst for IDC’s largest Wall Street clients including investment banking, VC’s, and mutual and hedge funds across every major financial region.

Over his career, Mr. Morales has authored and co-authored over 240 reports and studies in the area of semiconductors, mobile, PC, wireless, embedded, IoT, and IT marketplace. His team is responsible for some of the most interesting and evolving tech in our industry including coverage of microprocessors, accelerated computing, storage and memory,sensors and connectivity. His team has been responsible for initiating coverage of emerging technologies for IDC, and driving new research business practices, and creating leading industry market models in DRAM, NAND, Embedded processors and controllers, accelerated computing architectures, cellular baseband modems, WLAN, WiMAX, cellular broadband, digital consumer, foundry, EMS, intelligent systems, and overall semiconductors.

His career includes past postions with NEC Electronics and Dataquest.

EDUCATIONAL ACCOMPLISHMENTS

• B.S. in Finance and Accounting from San Jose State University
• Fluent in English and Spanish
• Frequent presenter and advisor to CEOs and executive teams across his portfolio of clients
• Strong reputation as an advisor and industry expert on Wall Street
• IDC executive analyst for Intel and Qualcomm
• Frequent speaker, presenter, and moderator at IDC Directions events in Asia and semiconductor industy conferences including ISS, GSA, CASPA, and SEMI

Joseph Chou

Business Development Manager, Scientech Corporation

Biography

Bio coming soon…

Vincent DiCaprio

Managing Director of Advanced Packaging, Applied Materials

Biography

Experienced in all facets of the technology sector, Vincent has over 30 years of outstanding achievement in Technology Development, Operations, Business, Sales and Marketing, having demonstrated success at companies like IBM, Amkor, ASE, TSMC, and GLOBALFOUNDRIES.

Currently leading Corporate and Business Development for the Advanced Packaging division at Applied Materials, he is responsible for forging new strategic alliances and partnerships key to technology advancement for future product solutions.    As Applied Material’s Strategic Advisor to the CEO of Tango Systems, Vincent guides this joint development effort executing multi-faceted global Go-To-Market strategies focused on addressing key technology and market inflections for new interconnect platforms.

With a degree in Pure and Applied sciences at Champlain Regional College, and a Bachelor of Engineering degree from Concordia University, Vincent is both the author and co-author of 30 Patents in the field of advanced semiconductor packaging.

For more information please visit: linkedin.com/in/vincentdicaprio

Geoffrey Stoddart

Commercial Director, Westerwood Global

Biography

Geoffrey joined Edwards back in 1984 and quickly became involved in the growing Semiconductor Market that Scotland enjoyed in the late 80’s. This exposure and learning led to opportunities to support Edwards equipment in the Far East, Geoffrey spent over 7 years in Asia living and working in Japan, Singapore, Taiwan and China.

Customers and Service have always been the focus of Geoffrey’s work in Edwards whether it was hands on in the early days to regional then global management and is now responsible for directing Edwards continued service growth as their Vice President Marketing – Semiconductor Service.

Sunil Banwari

Managing Director & COO, AT&S India

Biography

Mr Sunil Banwari is the Chief Operating Officer and Managing Director of AT&S India Pvt. Ltd. He has 30 years of international leadership experience including 20 years in US and 10 years in Asia in semiconductor and electronics manufacturing supporting automotive, consumer, computing. Military/aerospace, communications, networking and industrial applications. He has delivered top results in positions of increasing responsibility at Fortune500 companies like Intel Corp (20 yrs) and ON Semiconductor (7yrs) and other midsize companies including Smiths Interconnect and Neotech EMS. He is a multi-lingual with English, Hindi, Japanese, and Spanish and beginner German/Mandarin. He enjoys a high profile in Asia technology sector and is board member of Industry associations in China, India and Philippines. MS/MBA.

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Mustafa Pinarbasi is the CTO and Sr. Vice President of Magnetics Technology at Spin Memory (Previously Spin Transfer Technologies). Before joining Spin Memory in 2013, Dr. Pinarbasi was a CTO and SVP of Technology Development at SoloPower, Advanced Technology Department Manager at Hitachi GST and Distinguished Engineer at IBM. His accomplishments at IBM include the development of the giant magneto-resistance sensor used in the first GMR-based hard disk drives (HDD) and pioneering the adoption of ion beam sputtering technology into the read sensor production. He led the development of tunneling magneto-resistance (TMR) read head processing at Hitachi GST and the development of flexible and light weight solar panels at SoloPower. Dr. Pinarbasi holds a Ph.D. from the University of Illinois at Urbana-Champaign. He is an inventor with over 200 U.S. patents, has authored or co-authored over 30 scientific publications and has received numerous industry awards.

Mr. Ning Chen used to work in the mobile communication industry in Japan for long years. After joined Panasonic in 2003, he has been engaged in the development of advanced sensor solutions for smart systems. He is now the Director of China Technology Center of Industrial Solutions Company.

Ron, who joined CNW in early 2013 after over a decade at DHL, sees himself as customer-centric. He is available day and night to listen and help customers realize that CNW is their most reliable special logistics partner. Ron believes in open communications and making it easy for them to approach CNW with urgent and emergency shipping challenges, no matter how complicated.</span>

And as a big basketball fan and food connoisseur, Ron welcomes the opportunity to enjoy a good meal after a great game.

Hermann Waltl is currently the executive sales and customer support director for EV Group (EVG). In this role, he is responsible for overseeing EVG’s worldwide sales operations across all of the company’s product lines and key markets including Asia Pacific, Europe and North America. Waltl joined EV Group in 2002 as a sales operations manager where he was responsible for all aspects of worldwide contract management and sales administration for three years.

Prior to EVG, he held several management positions at Amdahl Deutschland GmbH (Amdahl Germany Ltd.), including most recently as director of professional services for Central Europe, and country manager for Switzerland and Austria. In this role, he oversaw an organization of 120 employees and provided consulting services to the IT industry. Before that, Waltl served as both a project manager and sales manager at Nixdorf Computer GmbH/Siemens Nixdorf Information Systems in Salzburg, Austria.

Waltl received a master of business administration degree, with an emphasis on business economics and strategic corporate management, from the University of Innsbruck, Austria.

Julio Coppo is currently serving the role of Vice President of Sales and Strategic Business Development for Nanotronics, a technology company that builds robotic, artificially intelligent industrial grade microscopes, including nSpec® and nSpec® 3D. nSpec®’s highly customizable software and hardware, enables these products to serve the semiconductor, material sciences, rubber, pharmaceutical and biotechnology industries. Julio joined Nanotronics in the Fall of 2016 and he oversees the global sales and customer outreach team.

Julio spends his personal time with his children and volunteering in youth enrichment programs such as Assistant Scout Master for Boy Scouts of America, and coaching youth ice hockey.

Previously Julio served as Regional Sales Manager at SUSS MicroTec, Strategic Account Manager for DCG Systems, and Sales and Applications Manager at Schlumberger Automated Test Equipment. Prior to Julio’s entry into the semiconductor industry, Julio served in the U.S. Navy as a Naval Flight Officer, patrolling the skies in the P-3, Orion, Submarine Hunter aircraft.