Abul Nuruzzaman

Abul Nuruzzaman is VP of Semiconductor Technology and IP Licensing at Adeia, Inc. (formally known as Xperi), San Jose, California. Prior licensing role, he led the marketing of Adeia’s hybrid bonding technology and semiconductor IP portfolio. Throughout his successful semiconductor industry career, Abul worked in product management, marketing and business development roles at AMD, Infineon (Cypress Semiconductor), TE Connectivity and Lattice Semiconductor. He holds BSEE degree from Osaka University, Japan, and MSEE degree from the University of California, Los Angeles (UCLA).

Hybrid Bonding: Innovation to Adoption

Hybrid bonding allows semiconductor wafers or individual die to be bonded with exceptionally fine-pitch (scalable to 1 micron) 3D electrical interconnects at low temperature without pressure or adhesives. Hybrid bonding was invented by a company called Ziptronix which was later acquired by Adeia (formally known as Xperi) in 2015. Since then, Adeia has continued to invest heavily in hybrid bonding R&D and supply chain enablement for production worthy wafer-to-wafer and die-to-wafer hybrid bonding processes. Adeia, a pioneer in hybrid bonding, has licensed numerous semiconductor companies to the bonding portfolio including Sony, SK hynix, Samsung, Micron, Kioxia, Western Digital, Qorvo, Canon, LAPIS, and UMC. Several of these companies engaged in a technology transfer program as well. Hybrid bonding technology was commercially adopted in stacked BSI image sensors, stacked 3D NAND memories, logic processors, and is anticipated to be adopted soon in HBM and RF front-end devices. In logic applications, a large die can be disaggregated into separate functions such as cache memory and processor. After disaggregation, the functional chiplets can be bonded on top of a core processor die to create a fully functional circuit. The hybrid bonding technology is a must-have tool to provide a multi-generational roadmap of products in high performance computing devices such as CPU, GPU, FPGA, SoC, other logic, memories, and 3D chiplet integrations.